High density interconnection (HDI) substrate patterning is typically performed with semi-additive patterning (SAP). SAP requires eight processing steps to form each dielectric layer. First, a dielectric material is formed over an existing layer. Vias are then etched through the dielectric layer to provide electrical connections to the lower layer. A seed layer is then deposited onto all exposed surfaces. In order to prevent metal deposition across the entire surface, a resist layer is formed over the exposed surfaces and then patterned. The patterning exposes only regions of the dielectric layer on which metal is desired in order to form contact lines and contact vias. Electroless plating then metalizes the exposed surfaces of the dielectric layer. The resist layer may then be removed. Finally, the seed layer that was formed over the regions that were not metallized is removed.